1. Field of the Invention
The present invention generally relates to data transfer systems and data transfer methods, and particularly relates to a DMA transfer system and DMA transfer method.
2. Description of the Related Art
A DMA (direct memory access) transfer system achieves high-speed data transfer by transferring data directly from a source to a destination without having an intervening CPU. FIG. 1 is a drawing showing an example of the configuration of a related-art DMA transfer system.
A DMA transfer system 10 shown in FIG. 1 includes a CPU 11, an interruption controller 12, a DMA controller 13, a memory 14, event counters 15-1 through 15-4, and bus interfaces 16-1 through 16-4. The CPU 11, the interruption controller 12, the DMA controller 13, and the memory 14 are coupled to each other via a bus 17. Further, the event counters 15-1 through 15-4 are coupled to the bus 17 through the respective bus interfaces 16-1 through 16-4.
The CPU 11 specifies a transfer source address, a transfer destination address, transfer data size, an increment/decrement of the transfer source address, an increment/decrement of the transfer destination address, etc., for DMA, thereby determining the settings of DMA transfer with respect to the DMA controller 13. In response, the DMA controller 13 performs the specified DMA transfer.
A description will be given below with respect to an example in which register data is transferred through DMA from the event counters 15-1 through 15-4 to the memory 14. Although the event counters are used as an example here, the operation of the DMA transfer remains the same even if macros having other functions are used.
The event counters 15-1 through 15-4 serve to count the pulses of data signals D0 through D4 during a period indicated by trigger signals TRG0 through TRG4, respectively. Namely, the event counter 15-1 starts counting the pulses of the data signal D0 when the trigger signal TRG0 becomes HIGH, and continues counting until the trigger signal TRG0 becomes LOW. When the counting comes to an end upon the change to LOW of the trigger signal TRG0, the count value is stored in an internal register of the event counter 15-1.
Upon completion of counting, the event counters 15-1 through 15-4 generate interruption signals INT0 through INT3. These interruption signals INT0 through INT3 are supplied to the interruption controller 12. In response to the interruption signals INT0 through INT3, the interruption controller 12 instructs the DMA controller 13 to start DMA transfer. In response, the DMA controller 13 performs DMA transfer.
FIG. 2 is a drawing showing the details of the event counters 15-1 through 15-4 and the bus interfaces 16-1 through 16-4 for the purpose of explaining DMA transfer operation. As shown in FIG. 2, the event counters 15-1 through 15-4 are provided with respective register sets 20-1 through 20-4. Further, the bus interfaces 16-1 through 16-4 include decoder selectors 21-1 through 21-4, respectively.
The register set 20-1 of the event counter 15-1 includes registers RA0, RB0, and RC0. The register set 20-2 of the event counter 15-2 includes registers RA1, RB1, and RC1. The register set 20-3 of the event counter 15-3 includes registers RA2, RB2, and RC2. The register set 20-4 of the event counter 15-4 includes registers RA3, RB3, and RC3. Each register is configured to store 8-bit data.
The bus 17 includes 32-bit address bus A[31:0], 2-bit control bus RW[1:0] for specifying write/read operation, and 32-bit data bus D[31:0]. As shown in the event counter 15-1, the data of the register RA0 corresponds to D[31:24] that represents bit 31 through bit 24 of the data bus. The data of the register RB0 corresponds to D[23:16] that represents bit 23 through bit 16 of the data bus. Further, the data of the register RC0 corresponds to D[15:8] that represents bit 15 through bit 8 of the data bus. Although illustration is omitted with respect to the event counters 15-2 through 15-4 due to the lack of space, the relationship between each of the register sets 20-2 through 20-4 and the data bus D[31:0] is the same as that of the register set 20-1.
With this configuration that assigns the registers RA0, RB0, and RC0 to the respective portions of the data bus D[31:0], it is possible to transfer all the data of the register set 20-1 at once by transferring 32-bit data on the D[31:0]. Accordingly, not only a DMA transfer that transfers 8-bit data three times, but also a DMA transfer that transfers 32-bit data only once, can be used for the purpose of transferring the data of the register set 20-1.
As shown in the event counter 15-1 and the bus interface 16-1, the registers RA0, RB0, and RC0 are allocated to addresses 0x1000, 0x1001, and 0x1002, respectively. Selecting a desired register by use of these addresses makes it possible to perform read access or write access to the selected register. By the same token, addresses 0x1004 through 0x1006 are allocated to the register set 20-2, addresses 0x1008 through 0x100A to the register set 20-3, and addresses 0x100C through 0x100E to the register set 20-4.
FIG. 3 is a drawing showing the allocation of the registers shown in FIG. 2 to the address space. As shown on the left-hand side of FIG. 3, the registers RA0, RB0, and RC0 are allocated to 0x1000, 0x1001, and 0x1002, respectively, the resisters RA1, RB1, and RC1 to 0x1004, 0x1005, and 0x1006, respectively, the resisters RA2, RB2, and RC2 to 0x1008, 0x1009, and 0x100A, respectively, and the resisters RA3, RB3, and RC3 to 0x100C, 0x100D, and 0x100E, respectively. This is the same as what is already described above.
It is assumed that the count values as previously described are stored as the data indicative of the results of counting in the RA0, RA1, RA2, and RA3 of the event counters 15-1 through 15-4. A case will then be examined below in which these count values are read out and transferred to addresses 0x2000 through 0x2003 in the memory 14 (FIG. 1). In such a case, the start address of the transfer source is set to 0x1000, the data transfer width to 8 bits, and an address increment at the transfer source to +4. These settings make it possible to perform DMA transfer with respect to the count values stored in the registers. This DMA transfer is performed by transferring 8-bit data four times.
In this case, the size of transfer data is 32 bits in total. Despite the fact that the data bus D[31:0] provides a 32-bit data width, however, a single 32-bit-width DMA transfer cannot be utilized in this case. This is because the addresses of the registers RA0, RA1, RA2, and RA3 are not arranged as consecutive addresses. Even if these addresses are arranged consecutively, these registers are all allocated to the same portion D[31:24] of the data bus, so that it is impossible to perform a 32-bit-width DMA transfer.
As another example, it is assumed that the count values as described above are stored as the data indicative of the results of counting in the registers RB0, RA1, RC2, and RA3 of the event counters 15-1 through 15-4. Address increments between the registers are +3, +6, and +2 in this case. Since the address increments are not constant, the DMA transfer that transfers 8-bit data four times cannot be performed. Further, because of the same reasons as in the previous case, the DMA transfer that transfers 32-bit data once cannot be performed. That is, no DMA transfer is possible in this case.
When there is a need to transfer the data of registers that are allocated to nonconsecutive or unequal-interval addresses, conventionally, data transfer is performed by CPU-based software operations. In the case of such software-based data transfer, all the four operation steps, i.e., setting of a read address, reading of data, setting of a write address, and writing of the data, need to be performed for each transfer action. Such transfer operation is thus extremely inefficient compared with DMA transfer, failing to achieve high-speed data transfer.
As a reference, Japanese Patent Application Publication No. 2001-256104 discloses a configuration for performing efficient access to nonconsecutive addresses.
Accordingly, there is a need for a DMA transfer system which can perform efficient DMA transfer with respect to data stored in the registers that are allocated to nonconsecutive or unequal-interval addresses.